1. Field of the Invention
The present invention relates to a semiconductor nonvolatile memory. In particular, the present invention relates to an electrically writable and erasable semiconductor nonvolatile memory (also referred to as the “EEPROM” or “electrically erasable and programmable read only memory”). Also, the present invention relates to a semiconductor device which has the semiconductor nonvolatile memory.
It should be noted here that the term “electrically writable and erasable semiconductor nonvolatile memory (EEPROM)” refers to a whole of semiconductor nonvolatile memories that are electrically writable and electrically erasable, and examples thereof include an EEPROM that is capable of performing erasing on a bit-by-bit basis and a flash memory. Also, unless being specified, the terms “nonvolatile memory” and “semiconductor nonvolatile memory” are used as synonyms for the term “EEPROM”. Also, the term “semiconductor device” refers to a whole of devices that function by utilizing semiconductor characteristics. Examples of the semiconductor device include a microprocessor, electrooptical devices such as a liquid crystal display device and a light-emitting device, and an electronic equipment in which there is installed a microprocessor or an electrooptical device.
2. Related Background Art
In recent years, an electrically writable and erasable semiconductor nonvolatile memory (EEPROM) (in particular, a flash memory) has drawn attention as a strong candidate for a memory that will replace a magnetic disk or a DRAM. In particular, a so-called multilevel nonvolatile memory, in which each memory element stores multi-state data more than binary data receives attention as a mass storage memory.
In the EEPROM, there are usually performed verify writing or verity erasing that includes an operation for confirming that a state after writing or erasing exists within a predetermined range. In particular, in a multilevel nonvolatile memory, it is required to control the state after writing or erasing with high precision, therefore such a verify operation becomes indispensable.
In a conventional verify writing/erasing operation, an operation period for performing writing/erasing for a certain period, and a reading period for confirming that the state after writing/erasing exists within a predetermined range, are alternately performed.
A manner in which the operation period and the reading period are alternately performed will be described with reference to FIGS. 2 and 3. FIG. 2 is a simplified block diagram in which a reading circuit 202 and writing/erasing circuit 201 are connected to a selected memory cell 203. A verify signal Sv is outputted from the reading circuit 202 and is inputted into the writing/erasing circuit 201. The writing/erasing circuit 201 performs writing/erasing by referring to the verify signal Sv. A procedure for verify writing/erasing is shown in FIG. 3. In FIG. 3, the reading circuit first operates (denoted as “active”) to perform reading. During this operation, the writing/erasing circuit does not operate (denoted as “not active”). The verify signal Sv outputted from the reading circuit becomes “Low” in the case where a read state of the memory cell differs from a target state. On the other hand, the verify signal Sv becomes “High” in the case where the read state of the memory cell coincides with the target state. In the case where the verify signal Sv is Low, the writing/erasing circuit starts its operation (becomes “active”) after the reading operation is finished, to perform writing/erasing for a certain period. Following this, reading is performed again and the state of the memory cell is compared with the target state. Then, in a like manner, if the verify signal Sv remains Low, writing/erasing is performed again for a certain period. At a point when the verify signal Sv becomes High after repeating these operations, the verify writing/erasing is finished. The conventional verify operation is performed in this manner.
The verify operation described above is an extremely effective means as a method of controlling the threshold voltage of a memory element with high precision. In particular, in the case of a multilevel nonvolatile memory that requires a narrow distribution width of the threshold voltage or in the case where the increases of variations are unavoidable due to the miniaturization, the verify operation is indispensable. However, the conventional verify operation necessitates the repetition of writing/erasing and reading, which leads to a problem that this verify operation essentially takes long time in comparison with a single operation in which reading is not performed. Further, an operation voltage in the writing/erasing becomes high in comparison with a case of reading, and the writing/erasing may require pre-charging or pre-discharging depending on which reading scheme is used. This causes a further reduction in the speed of the verify operation.
That is, there arises a problem due to the variations of a threshold voltage in the single operation, and there arises a problem due to an operation speed in the verify operation. As a result, performing a high-speed operation with a narrow distribution width of the threshold voltage becomes an important subject in order to improve the performance of a nonvolatile memory.
The present invention has been made in the light of the problems described above. An object of the present invention is to provide a nonvolatile memory that enables high-speed writing/erasing with a narrow distribution width of a threshold voltage. In more detail, an object of the present invention is to provide a verify method that realizes a high-speed operation by shortening a verify operation time and a nonvolatile memory using the verify method. Also, an object of the present invention is to provide a semiconductor device which has such a nonvolatile memory.